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NXP Semiconductors /LPC18xx /RTC /CCR

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Interpret as CCR

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (DISABLED)CLKEN 0 (NO_EFFECT)CTCRST 0RESERVED 0 (ENABLED)CCALEN 0RESERVED

CCALEN=ENABLED, CLKEN=DISABLED, CTCRST=NO_EFFECT

Description

Clock Control Register

Fields

CLKEN

Clock Enable.

0 (DISABLED): The time counters are disabled so that they may be initialized.

1 (ENABLED): The time counters are enabled.
CTCRST

CTC Reset.

0 (NO_EFFECT): No effect.

1 (RESET): When one, the elements in the internal oscillator divider are reset, and remain reset until CCR[1] is changed to zero. This is the divider that generates the 1 Hz clock from the 32.768 kHz crystal. The state of the divider is not visible to software.
RESERVED

Internal test mode controls. These bits must be 0 for normal RTC operation.
CCALEN

Calibration counter enable.

0 (ENABLED): The calibration counter is enabled and counting, using the 1 Hz clock. When the calibration counter is equal to the value of the CALIBRATION register, the counter resets and repeats counting up to the value of the CALIBRATION register. See Section 29.6.6.2 and Section 29.7.1.

1 (DISABLED): The calibration counter is disabled and reset to zero.
RESERVED

Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined.

Links

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Register Reference

https://github.com/cmsis-svd/cmsis-svd-data